Semiconductor devices are found in many products in the fields of entertainment, communications, networks, computers, and household markets. Semiconductor devices are also found in military, aviation, automotive, industrial controllers, and office equipment. The semiconductor devices perform a variety of electrical functions necessary for each of these applications.
The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each semiconductor die contains hundreds or thousands of transistors and other active and passive devices performing a variety of electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation.
One goal of semiconductor manufacturing is to produce a package suitable for faster, reliable, smaller, and higher-density integrated circuits (IC) at lower cost. Flip chip packages or wafer level chip scale packages (WLCSP) are ideally suited for ICs demanding high speed, high density, and greater pin count. Flip chip style packaging involves mounting the active side of the die face down toward a chip carrier substrate or printed circuit board (PCB). The electrical and mechanical interconnect between the active devices on the die and conduction tracks on the carrier substrate is achieved through a solder bump structure comprising a large number of conductive solder bumps or balls. The solder bumps are formed by a reflow process applied to solder material deposited on contact pads, which are disposed on the semiconductor substrate. The solder bumps are then soldered to the carrier substrate. The flip chip semiconductor package provides a short electrical conduction path from the active devices on the die to the carrier substrate in order to reduce signal propagation, lower capacitance, and achieve overall better circuit performance.
In many applications, it is desirable to vertically stack semiconductor die for greater device integration and minimize interconnect routing. The electrical interconnection between stacked semiconductor die has been done by using through hole vias which traverse from a front side to the backside of the die. The through hole vias are formed by drilling through the active area of the die or through saw streets on the wafer prior to any dicing operation. The through hole vias are filled with conductive material. The process of drilling through hole vias in the active area of the die or in saw streets on the wafer can cause damage to the wafer and/or die.
One example of using through hole vias is shown in US patent publication US20070269931. The reference shows a structure and fabrication method for a wafer level package with trenches formed on the backside of wafer to expose the through hole vias. The recessed via design uses a substantial portion of the silicon, which reduces die area for circuitry and limits the number of via that can be formed in practice. In addition, the recessed vias are disposed in close proximity to die area circuitry, which increases parasitic capacitance.